Algorithm of rational processor architecture

A New Reachability Algorithm for Symmetric Multi-processor Architecture

Partitioned BDD-based algorithms have been proposed in the literature to solve the memory explosion problem in BDD-based verification. A naive parallelization of such algorithms is often ineffective as they have less parallelism. In this paper we present a novel parallel reachability approach that lead to a significantly faster verification on a Symmetric Multi-Processing architecture over the ...

Algorithm architecture trade offs in network processor design

The increasing use of computer networks for all kinds of information exchange between autonomous computing resources is associated with a number of sideeffects. In the Internet, where computers all over the globe are interconnected, the traffic volume grows faster than the infrastructure improves, leading to congestion of networking routes. In the application domain of embedded systems, network...

Efficient Algorithm and Architecture for Elliptic Curve Cryptographic Processor

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field ...

Counterrow Pipeline Processor Architecture Counterrow Pipeline Processor Architecture

The counter ow pipeline processor architecture (cfpp) is a proposal for a family of microarchitectures for risc processors. The architecture derives its name from its fundamental feature, namely that instructions and results ow in opposite directions within a pipeline and interact as they pass. The architecture seeks geometric regularity in processor chip layout, purely local control to avoid p...

Stream Processor Architecture